A modern integrated circuit can include multiple power domains that receive different supply signals. Multiple level shifting circuits are located at the boundaries between different power domains and are connected to inputs/outputs of logic circuits that are positioned near these boarders.
Prior art level shifters are slow and introduce delay as a high to low switch or a low to high switch involves passing through a conjunction state, when both NMOS and PMOS transistors in same current path are in some conduction mode. This is a very critical for today's designs, where clock cycle time is comparable to delay of several “digital” cells.